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74AUP2G02
74AUP2G02
主要參數(shù)

The 74AUP2G02 is a dual 2-input NOR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM JESD22-A114F Class 3A exceeds 5000 V

    • MM JESD22-A115-A exceeds 200 V

    • CDM JESD22-C101E exceeds 1000 V

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD78B Class II

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial power-down mode operation

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C


參數(shù)類型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AUP2G02DCProduction0.8 - 3.6CMOS± 1.98.3702ultra low-40~12520334.1113VSSOP8
74AUP2G02GNProduction0.8 - 3.6CMOS± 1.98.3702ultra low-40~12523810.6148XSON8
74AUP2G02GSProduction0.8 - 3.6CMOS± 1.98.3702ultra low-40~12527610.8146XSON8
74AUP2G02GTProduction0.8 - 3.6CMOS± 1.98.3702ultra low-40~1253276.1157XSON8